A radio communication LSI consists of a high frequency (RF) LSI and a baseband (BB) LSI. The high frequency LSI processes signals received by an antenna as analog signals. The baseband LSI processes transmission signals as digital signals before modulation or after demodulation.
And when in high speed synchronous communications between the high frequency LSI and the baseband LSI configured as described above, sometimes such troubles as signal delays and jittering occur in the transmission path. At this time, if communications are made according to clock signals that are asynchronous between those LSIs, the receiving side LSI often fails in correct receiving of data. This has been a problem. To avoid this problem, therefore, the receiving side LSI is required to control the clock phase used to receive data so as to receive the object data correctly. Japanese Patent No. 3490078 and Japanese Patent No. 3792904 disclose examples of how such a receiving LSI controls the clock phase to receive data respectively.
In case of the baseband signal receiving circuit disclosed in Japanese Patent No. 3490078, plural clock phases are used to sample the sync word included in each inputted baseband signal to determine a sampling clock phase according to the number of clock phase change points when the baseband signal generates a change point at its rising or falling. Then, the receiving circuit uses the determined sampling clock to sample the object baseband signal, thereby enabling the symbol of the baseband signal (serial signal) to be demodulated correctly.
In case of the receiving unit disclosed in Japanese Patent No. 3792904, which describes its related techniques, upon receiving the preamble part of an object transmission signal, the receiving unit uses a high speed clock to sample the object signal. And upon receiving the data part that follows the preamble part, the receiving unit switches the high speed clock to a low speed clock. The receiving unit can thus reduce the power consumption required by over-sampling.